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Features
* * * * * * * * *
Very Low Power Design Single IF Architecture Excellent Noise Performance 1-bit ADC on Chip Small QFN Package (4 mm x 4 mm, 24 Pins) Highly Integrated, Few External Components Advanced BiCMOS Technology (UHF6s) Supply Switch for External Circuitry (e.g., TCXO) Non-ESD-sensitive Device
1. Description
The ATR0603 is a single-IF GPS front-end IC, designed to meet the requirements of mobile and automotive applications. Excellent RF performance combined with high bandwidth and a low noise figure enables high-quality GPS solutions, and its very low power consumption is a perfect match for portable devices. Featuring a fully integrated balanced frequency synthesizer, only a few external components are required. The gain of the IF amplifier can be set to three different levels in order to meet the requirements for various applications. Several types of external oscillators can be connected to the robust TCXO interface. The startup logic allows significant power saving due to very low power-down current and the ability to disable the external TCXO or even other external components. CMOS output drivers deliver a 1-bit data signal and a 16.367667-MHz clock signal to the baseband interface. Figure 1-1.
PU
GPS Front-end IC ATR0603 Preliminary
Block Diagram
BP NBP BPI NBPI AMP1 AMP2
Startup logic
GND
VCC
ATR0603
A D
VDIG
RF SIG
NRF XSUP VCO PLL
XIN SC
XREF
4950B-GPS-11/06
2. Pin Configuration
Figure 2-1. Pinning QFN24 (4 mm x 4 mm)
VDIG SC SIG PU VCC AMP2 24 23 22 21 20 19 GND GND XREF XIN GND XSUP 1 2 3 4 5 6 18 17 16 15 14 13 AMP1 NBPI BPI NBP BP VCC Paddle GND 7 8 9 10 11 12 VCC MO GND NRF RF TEST
Table 2-1.
Pin Paddle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Notes:
Pin Description
Symbol GND GND GND XREF XIN GND XSUP VCC MO GND NRF RF TEST VCC BP NBP BPI NBPI AMP1 AMP2 VCC PU SIG SC VDIG Type(1) S S S A_I A_I S XS S A_O S A_I A_I D_I S A_O A_O A_I A_I D_I D_I S D_I D_O D_O S Function Common ground Ground Ground TCXO interface ground TCXO interface signal Ground External circuitry supply switch Analog supply Test buffer output (fIF) Ground Complementary RF input RF input Enable test buffer Analog supply IF filter interface (mixer output, open collector) IF filter interface (complementary mixer output, open collector) IF filter interface (IF input) IF filter interface (complementary IF input) IF gain control bit #1 IF gain control bit #2 Analog supply Power-up signal input Data output Sample clock Digital supply
1. Type: A_I = Analog input, A_O = Analog output, D_I = Digital input, D_O = Digital output, S = Supply, XS = External supply
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ATR0603 [Preliminary]
3. Functional Description
3.1 General Description
The ATR0603 GPS receiver IC has been especially designed for GPS applications in both mobile phone and automotive applications. From this system point of view, it incorporates highest isolation between GPS and cellular bands, as well as very low power consumption. The L1 input signal (fRF) is a direct sequence spread spectrum (DSSS) signal with a center frequency of: fRF = 1575.42 MHz. The digital modulation scheme is bi-phase shift keying (BPSK) with a chip rate of 1.023 Mbps. As the input signal power at the antenna is approximately -140 dBm, the desired signal is below the thermal noise floor.
3.2
Startup Logic
The startup logic ensures reliable operation within the recommended operating conditions. The external power control signal PU is passed through a Schmitt trigger input to eliminate voltage ripple and prevent undesired behavior during startup and shutdown. This block includes a switch to supply external circuits, for example, the TCXO. This switch is controlled by the power control signal PU.
3.3
TCXO Interface
This receiver is designed for use with an external TCXO. The TCXO output signal is fed to a balanced input buffer. The recommended reference frequency is: fTCXO = 16.367667 MHz. Connecting the supply pin of the TCXO to the XSUP pin of ATR0603 allows for a power down of the TCXO when the ATR0603 is shut off (see Section 3.2).
3.4
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no external components are required. The VCO combines very good phase noise behavior and excellent spurious suppression. The relation between the reference frequency (fTCXO) and the VCO center frequency (fVCO) is given by: fVCO = fTCXO x 90 = 16.367667 MHz x 90 = 1473.09003 MHz.
3.5
RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first bandpass filtering of the signal. For the LNA, Atmel(R)'s ATR0610 is recommended, due to its low noise figure, high linearity and low power consumption. The output of the LNA drives a SAW filter, which provides image rejection for the mixer and the required isolation of all GSM bands. The output of the SAW filter is fed into a highly linear mixer with high conversion gain and excellent noise performance. The IF frequency (fIF) is given by: fIF = fRF - fVCO = 1575.42 MHz - 1473.09003 MHz = 102.32997 MHz.
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3.6
IF Filter
The mixer directly drives an external LC bandpass filter via open collector outputs. In order to provide highest selectivity and conversion gain, it is recommended to design the external filter, according to the application proposal in chapter 10, as a 2-pole filter with a quality factor Q > 25.
3.7
IF Amplifier
The output of the IF filter drives an IF amplifier which is combined with additional low-pass filtering. The gain of this amplifier can be set to three different levels in order to optimally charge the input of the following analog-to-digital converter for each application. The gain is internally set to high gain mode but can be adjusted by using external pull-down resistors at pin 18 (AMP1) and pin 19 (AMP2). If high gain mode is desired, pins 18 and 19 have to be left floating (see Section 8. "Electrical Characteristics" ).
3.8
A/D Converter
The analog-to-digital converter stage has a total resolution of 1 bit. It comprises a sub-sampling unit, clocked by the reference frequency (fTCXO). The frequency spectrum of the digital output signal (fOUT), present at the data output SIG, is then given by: fOUT = fIF - fTCXO x n . The selected sub-sampling factor (n = 6) leads to the designated digital output signal, with a center frequency given by: fOUT = fIF - fTCXO x 6 = 102.32997 MHz - 16.367667 MHz x 6 = 4.123968 MHz.
3.9
Clock and Data Driver
CMOS output drivers provide the output bit as well as the system clock to the baseband IC. The amplitude of this signal strongly depends on the value for the digital supply voltage (see Section 8. "Electrical Characteristics" on page 7).
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ATR0603 [Preliminary]
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ATR0603 [Preliminary]
4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Analog supply voltage Digital supply voltage Input voltage Max. supply voltage difference: (VDIG - VCC) Max. supply voltage difference: (VPU - VCC) Operating temperature Storage temperature Symbol VCC VDIG Vin VDIG VPU Top Tstg Value -0.3 to +3.7 -0.3 to +3.7 -0.3 to +3.7 0.5 0.5 -40 to +85 -55 to +125 Unit V V V V V C C
5. Thermal Resistance
Parameters Thermal Resistance Symbol Rth Value 45 Unit K/W
6. Operating Range
Parameters Analog supply voltage Digital supply voltage Temperature range Input frequency Reference frequency Symbol VCC VDIG Temp fRF fTCXO Value 2.6 to 3.6 1.6 to 3.6 -40 to +85 1575.42 16.3 to 16.4 Unit V V C MHz MHz
7. ESD Characteristics
Parameters ESD level HBM (Human Body Model) ESD level MM (Machine Model) ESD level CDM (Charged Device Model) Symbol VHBM VMM VCDM Used Norm ESD-STM5.1-2001 JESD22-A114D 2006 AEC-Q100-002-Ref-D EIA/JESD22 A115 A ESD-STM.5.3.1-1999 Value 4000 300 1000 Unit V V V
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8. Electrical Characteristics
Temperature = +25C Minimum/maximum limits are at +25C ambient temperature, unless otherwise specified. No. 1 1.1 Parameters Common Analog supply current VCC = 3.6V, VDIG = 1.6V, VPU = 1.6V VCC = 2.6V, VDIG = 1.6V, VPU = 1.6V VCC = 3.6V, VDIG = 1.6V, VPU = 1.6V VCC = 2.6V, VDIG = 1.6V, VPU = 1.6V 7, 13, 20 7, 13, 20 14, 15, 16, 17 14, 15, 16, 17 IS 10.5 mA A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.2
Analog supply current
IS
9
mA
A
1.3
Mixer core current
IBP
1.5
mA
A
1.4
Mixer core current
IBP
1.4
mA
A
1.5
VCC = 3.6V, Digital supply current(1) VDIG = 3.3V, VPU = 1.6V VCC = 2.6V, Digital supply current(1) VDIG = 1.6V, VPU = 1.6V Supply current in power-down mode Noise figure (SSB) Mixer Output frequency Input impedance (balanced) Conversion gain Noise figure (SSB) IF Amplifier IF gain0 IF gain1 IF gain2 IF gain3 AMP1 = AMP2 = low AMP1 = X , AMP2 = low AMP1 = low, AMP2 = X AMP1 = AMP2 = X
(2)
24
IDIG
1.4
mA
A
1.6
24 7, 13, 14, 15, 16, 17, 20, 24
IDIG
1.0
mA
A
1.7
VPU = VPU,off
IPD NFtot 8 102.32997 10 - j80 20 6.8 28 42 42 56
5
A
A
1.8 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 Notes:
dB MHz dB dB dB dB dB dB
C A C B C D D D D
fTCXO = 16.367667 MHz fRF = 1575.42 MHz Recommended IF filter
14, 15 10, 11 8 8 18, 19 18, 19 18, 19 18, 19
fIF Z11 GMIX NFMIX GIF0 GIF1 GIF2 GIF3
*) Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Capacitive load (CL = 10 pF) at pins 22, 23 2. X represents a pin left floating (internal pull up)
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ATR0603 [Preliminary]
4950B-GPS-11/06
ATR0603 [Preliminary]
8. Electrical Characteristics (Continued)
Temperature = +25C Minimum/maximum limits are at +25C ambient temperature, unless otherwise specified. No. 4 4.1 4.2 4.3 4.4 4.5 4.6 5 5.1 5.2 5.3 Parameters Clock and Data Driver Clock driver frequency Clock input level Clock output level, low Data output level, high Data output level, low Startup Logic Voltage level power-on Voltage level power-off Voltage level at XSUP Ixsup = 2 mA, VPU = VPU,on 21 21 6 VPU,on VPU,off VXSUP (VCC - 0.1) 1.4 0.8 V V V A A A fTCXO = 16.367667 MHz fTCXO = 16.367667 MHz Cload.max = 10 pF Cload,max = 10 pF Cload,max = 10 pF 23 3, 4 23 23 22 22 fCLK VTCXO VCLK,high VCLK,low VData,high VData,low 0.1 16.367667 0.5 0.9 x VDIG 0.1 x VDIG 0.9 x VDIG 0.1 x VDIG MHz Vpp V V V V A D B B B B Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Clock output level, high Cload,max = 10 pF
*) Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Capacitive load (CL = 10 pF) at pins 22, 23 2. X represents a pin left floating (internal pull up)
9. Output Interface
Figure 9-1. Data Output SIG Is Valid with Rising Edge of Sample Clock SC
SIG SC
T = 1/16.367667 MHz
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4950B-GPS-11/06
10. Application Circuit
Figure 10-1. Application Example
VCC
68 10 nF VDIG 100 nF 100 nF VCC 220 nH 4.3 pF 21 PU 14 BP 15 NBP 16 BPI 220 nH 220 nH 4.3 pF 17 NBPI 18 AMP1 19 AMP2 VCC LNA section (opt.) VCC PU Startup logic 7 220 nH VCC 13 VCC GND 10 nF 1.3 pF 47 pF 4.7 nH 5.6 nH 1.5 pF ATR0610 SAW B4060 11 RF A D NRF XSUP VCO PLL SIG 22 Data out 20
PU
ATR0603
VDIG
24
1.3 pF
10 6
4 100 nF TCXO
XIN SC 23 Sample clock
3
XREF TEST 12 MO 8
Note:
See also the recommended IF filter layout, shown in Figure 10-2 on page 9.
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ATR0603 [Preliminary]
4950B-GPS-11/06
ATR0603 [Preliminary]
Figure 10-2. Recommended IF Filter: Layout versus Schematic
14 15 16 17
14
15
16
NBPI 17 Cb Lf
NBP
Ca
Cb
BP
Lc
Ld
Ca
B
Lc Ld Le
Le
Lf
A
VCC
Note:
Mutual inductance between the four inductors Lc to Lf plays an important role in the IF filter characteristics. In any design, the layout arrangement shown in Figure 10-2 should be followed as closely as possible. Measurements: A = 2.8 mm; B = 1.4 mm Lc to Lf: Wire-wound SMD inductors, size 0603 (see Table 11-1 on page 11)
Table 10-1.
Parameter
Specifications of Recommended TCXO (Rakon; IT5325BE 16.367667 MHz)
Comment Nominal frequency referenced to 25C Within operating temperature range Operating temperature range DC-coupled clipped sine wave 0.8 1.5 9 11 V mA pF At maximum supply voltage Tolerable load capacitance -40 Min. Nominal 16.367667 2.5 85 Max. Unit MHz ppm C
Nominal frequency Frequency deviation Temperature range Output waveform Current Output load capacitance
Output voltage (peak to peak) At minimum supply voltage
BPI
9
4950B-GPS-11/06
11. Demonstration Board
Figure 11-1. Schematic of Demonstration Board (Without LNA Section)
C34 VCC VDIG VCC1 R1 C1 7 VCC3 13 C7 J1 L4 L3 C4 14 BP R2 Startup logic C2 12 TEST C35 P2 FI1 P1 6 IN NIN OUT NOUT 2 L7 5 1 C18 10 6 XO2 C31 1 4 3 2 4 XREF 3 NRF XSUP XIN SC 23 1 2 J2 VCO/PLL 1473.09003 MHz AMP1 AMP2 18 19 A D SIG 22 1 2 C12 11 RF J3 15 NBP 16 BPI L2 L1 C3 17 NBPI 21 PU J4 VCC4 20 C23 VCC2 24 + + C35 2 3 J5
1 2 3
1 2 3
MO
8
10
ATR0603 [Preliminary]
4950B-GPS-11/06
ATR0603 [Preliminary]
Table 11-1.
Qty 2 3 1 2 2 1 2 1 1 4 1 1 0 1p3 4p3 0p1 5n6 2% Multilayer 10 10n 68 100n 100p 142-0711-821
Bill of Materials for the Demonstration Board (Without LNA Section)
Value Parts J2, J3 J1, J4, J5 R2 C12, C18 C3, C4 L7 C5, C34 C1 R1 C2, C7, C23, C31 C35 P1 L1, L2, L3, L4 IC1 FI1 XO2 P2 2.0 ppm 0.1 pF 0.1 pF 2% 20% 5% 5% 20% 5% 16V 25V Y5V C0G 16V 16V X7R 16V C0G C0G Tolerance Voltage Material Manufacturer Molex(R) Molex Vishay(R) Taiyo Yuden Murata
(R) (R)
Manufacturer Order Code 90120-0762 90120-0763 CRCW0402000Z EVK105CH1R3BW GRM1555C1H4R3GZ01B 744784056G 293D106X0016B2 VJ0402Y103JXJ CRCW0402680J VJ0402V104MXJ VJ0402A101JXXA. 142-0711-821 0603CS-R22XGB 744761222G ATR0603 B39162-B4060-U810 IT5325BE Ref. no. 34365 125426
Wurth(R) Elektronik Vishay Vishay Vishay Vishay Vishay Johnson ComponentsTM
4 1 1 1 1
220n 2% ATR0603-PFQW B4060 IT5325BE 16.367667 MHz R125426
2%
Coilcraft(R) alternatively Wurth Elektronik Atmel Epcos
(R)
Rakon Radiall(R)
Figure 11-2. Photo of Evaluation Board (Including LNA Section)
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4950B-GPS-11/06
12. Recommended Footprint (QFN24 - 4 mm x 4 mm)
Figure 12-1. Recommended Footprint
0.30 0.4 x 0.4 (16 x) solder stop opening 0.25 (9 x)
2.6 x 2.6 metal pad Pads 0.8 x 0.28 (24 x) solder stop overlap 0.05 0.50 All dimensions in mm Scale 10 : 1
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ATR0603 [Preliminary]
13. Ordering Information
Extended Type Number ATR0603-PFQW Package QFN24 - 4 mm x 4 mm Remarks Taped and reeled
14. Package Information
Package: QFN_ 4 x 4_24L Exposed pad 2.6 x 2.6 Dimensions in mm Not indicated tolerances 0.05 24 1 Pin1 identification 6 13 6 12 7 0.5 nom. 2.5 Top 18 Bottom 2.60.15 19 24 1
4
0.2 0.90.1
Z
0.40.1
Z 10:1
Drawing-No.: 6.543-5123.01-4 Issue: 1; 28.11.05 0.230.07
technical drawings according to DIN specifications
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4950B-GPS-11/06
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4950B-GPS-11/06

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